1. Field of the Invention
The present invention relates to a process for improving the silicide sheet resistance of titanium silicide formed upon silicon. Specifically, fluorine is implanted into N+ doped regions of silicon and annealed under a cap oxide, resulting in enhancement of nucleation site density for the subsequent transformation into C-54 phase titanium silicide.
2. Description of the Related Art
With the decreased size of semiconductor devices, the sheet resistivity of the electrically-conducting structures of these devices, such as the gates of MOS transistors, emitters of bipolar transistors, local interconnect regions of MOS and bipolar transistors, and interconnect lines connecting these devices together, is beginning to limit the speed of operation.
One well-known technique for reducing sheet resistivity is to form a layer of metal silicide over these electrically-conducting structures. The resulting silicided structures provide the lower resistivity of a metal silicide, along with the well-known attributes of silicon.
TiSi.sub.2 is one of the most extensively utilized metal silicides. A major problem with forming TiSi.sub.2, however, is that sheet resistance increases strongly for N+-doped silicon with decreasing linewidth. The relationship between sheet resistance and linewidth for TiSi.sub.2 is shown in FIG. 1.
At least two distinct phases of TiSi.sub.2 have been recognized. These phases are known as C-49 and C-54. C-49 TiSi.sub.2 exhibits substantially higher sheet resistance than the C-54 phase. FIG. 1 can therefore be explained by a nucleation and growth model.
FIG. 2 illustrates this nucleation and growth model. As shown in FIG. 2A, C-49 phase 1 is initially formed upon the surface of linewidth 2, along with C-54 nucleation sites 3. FIG. 2B shows that upon further reaction, C-54 phase 4 grows at nucleation sites 3. FIG. 2C shows the ultimate result wherein growth areas of C-54 phase 4 merge to form a continuous region of C-54 having lower sheet resistance. Because C-54 phase nucleation site density is dependent upon linewidth, narrower linewidths yield fewer nucleation sites from which the lower resistive C-54 phase can grow.
Improved processes have been proposed to promote formation of TiSi.sub.2 having low sheet resistances. Sakai, et al. (1992 VLSI Tech. Dig. 66) describe implanting As into both the N+ and P+ regions of a CMOS structure prior to silicide metal implantation, causing pre-amorphization of the silicon. Titanium is then applied to the amorphous silicon, followed by a sequential two-step sintering process in which C-49 phase is created and converted into C-54 phase. Fujii, et al. (1995 VLSI Tech. Dig. 57) describe enhancement of the Sakai process utilizing high-temperature sputtering of titanium.
Several groups have investigated the physical basis underlying these pre-amorphization techniques. Chen, et al. (1996 Mat.Res.Symp.Proc. 89) suggest that pre-amorphization does not increase the rate of conversion of C-49 to C-54, but instead enhances the reaction rate between Ti and loosely bound amorphous silicon, resulting in C-54 having larger grains and lower resistivity. Kittl, et al. (1996 VLSI Tech. Dig. 14) suggest that pre-amorphization causes formation of C-49 silicide having a grain size smaller than the linewidth. Xiao, et al. (1990 Mat.Res.Soc.Proc. 167) have suggested that pre-amorphization utilizes latent energy stored in amorphous silicon to enhance the kinetics of the C-54 phase transformation reaction.
The pre-amorphization techniques discussed above have been somewhat successful in lowering sheet resistance on silicided surfaces. However, pre-amorphization techniques remain experimental. The process in accordance with the present invention utilizes the conventional siliciding process with the addition of a single fluorine implant step to enhance formation of C-54 phase titanium silicides at the extremely narrow linewidths demanded by modern devices.